Packaging of an IC chip or die often entails, in part, fabrication of electrically-isolated interconnect features through formation of patterned layers of metal and patterned layers of electrically-insulating or dielectric material (which may be referred to as build-up, or build-up material). The interconnect features may provide pathways for electrically-conductive pads on the chip to connect electrically to an external interface of the package containing the fabricated IC chip. The interconnect features may also break-out the points of electrical connection from being over or above some areas of the IC chip (e.g., the pads, which may be located in central regions or densely packed regions of the IC chip) to positions scaled for the electrical interface of the package. The interconnect features may accordingly be referred to as electrical Redistribution Layer (eRDL) features.